Altium

Design Rule Verification Report

Date: 08.05.2019
Time: 12:42:00
Elapsed Time: 00:00:00
Filename: G:\WORKSPACE\ALTIUM\OZON\Detektory\Detektory.PcbDoc
Warnings: 0
Rule Violations: 46

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.6mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.5mm) (Max=1mm) (Preferred=1mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 4
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) 30
Silk to Silk (Clearance=0.254mm) (All),(All) 12
Net Antennae (Tolerance=0mm) (All) 0
Room Detektory (Bounding Region = (29.845mm, 26.797mm, 215.9mm, 125.476mm) (InComponentClass('Detektory')) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 46

Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Hole Size Constraint: (3.7mm > 2.54mm) Pad DET_MEAS-0(90.136mm,73.6mm) on Multi-Layer Actual Hole Size = 3.7mm
Hole Size Constraint: (3.7mm > 2.54mm) Pad DET_MEAS-0(90.136mm,98mm) on Multi-Layer Actual Hole Size = 3.7mm
Hole Size Constraint: (3.7mm > 2.54mm) Pad DET_REF-0(71.135mm,73.7mm) on Multi-Layer Actual Hole Size = 3.7mm
Hole Size Constraint: (3.7mm > 2.54mm) Pad DET_REF-0(71.135mm,98.1mm) on Multi-Layer Actual Hole Size = 3.7mm

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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.152mm < 0.254mm) Between Pad C5-1(80.85mm,118mm) on Top Layer And Text "IC1" (78mm,115.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.152mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C5-2(78.15mm,118mm) on Top Layer And Text "IC1" (78mm,115.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-2(76.38mm,111mm) on Multi-Layer And Track (76.634mm,109.501mm)(76.634mm,109.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-2(76.38mm,111mm) on Multi-Layer And Track (76.634mm,112.041mm)(76.634mm,112.448mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-3(76.38mm,108.46mm) on Multi-Layer And Track (76.634mm,106.961mm)(76.634mm,107.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-3(76.38mm,108.46mm) on Multi-Layer And Track (76.634mm,109.501mm)(76.634mm,109.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-4(76.38mm,105.92mm) on Multi-Layer And Track (76.634mm,104.65mm)(76.634mm,104.879mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-4(76.38mm,105.92mm) on Multi-Layer And Track (76.634mm,106.961mm)(76.634mm,107.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-5(84mm,105.92mm) on Multi-Layer And Track (83.746mm,104.65mm)(83.746mm,104.879mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-5(84mm,105.92mm) on Multi-Layer And Track (83.746mm,106.961mm)(83.746mm,107.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-6(84mm,108.46mm) on Multi-Layer And Track (83.746mm,106.961mm)(83.746mm,107.419mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-6(84mm,108.46mm) on Multi-Layer And Track (83.746mm,109.501mm)(83.746mm,109.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-7(84mm,111mm) on Multi-Layer And Track (83.746mm,109.501mm)(83.746mm,109.959mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-7(84mm,111mm) on Multi-Layer And Track (83.746mm,112.041mm)(83.746mm,112.499mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-8(84mm,113.54mm) on Multi-Layer And Track (83.746mm,112.041mm)(83.746mm,112.499mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.252mm < 0.254mm) Between Pad IC1-8(84mm,113.54mm) on Multi-Layer And Track (83.746mm,114.581mm)(83.746mm,114.81mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.252mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad R1-1(96.807mm,117.5mm) on Multi-Layer And Track (94.775mm,117.5mm)(95.791mm,117.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad R1-2(86.647mm,117.5mm) on Multi-Layer And Track (87.663mm,117.5mm)(88.679mm,117.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R3-1(88.5mm,103.42mm) on Multi-Layer And Text "DET_MEAS" (98.813mm,102.838mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad R3-1(88.5mm,103.42mm) on Multi-Layer And Track (88.5mm,104.436mm)(88.5mm,105.452mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm]
Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad R3-2(88.5mm,113.58mm) on Multi-Layer And Track (88.5mm,111.548mm)(88.5mm,112.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad R4-1(63.42mm,117mm) on Multi-Layer And Track (64.436mm,117mm)(65.452mm,117mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad R4-2(73.58mm,117mm) on Multi-Layer And Track (71.548mm,117mm)(72.564mm,117mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad R6-1(109.04mm,106.5mm) on Multi-Layer And Track (107.008mm,106.5mm)(108.024mm,106.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad R6-2(98.88mm,106.5mm) on Multi-Layer And Track (99.896mm,106.5mm)(100.912mm,106.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad R7-1(70mm,114.08mm) on Multi-Layer And Track (70mm,112.048mm)(70mm,113.064mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm]
Silk To Solder Mask Clearance Constraint: (0.179mm < 0.254mm) Between Pad R7-2(70mm,103.92mm) on Multi-Layer And Text "DET_REF" (79.797mm,102.948mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.179mm]
Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad R7-2(70mm,103.92mm) on Multi-Layer And Track (70mm,104.936mm)(70mm,105.952mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm]
Silk To Solder Mask Clearance Constraint: (0.247mm < 0.254mm) Between Pad R8-1(52.42mm,106.5mm) on Multi-Layer And Track (53.436mm,106.5mm)(54.452mm,106.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.247mm]
Silk To Solder Mask Clearance Constraint: (0.223mm < 0.254mm) Between Pad R8-2(62.58mm,106.5mm) on Multi-Layer And Track (60.548mm,106.5mm)(61.564mm,106.5mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.223mm]

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Silk to Silk (Clearance=0.254mm) (All),(All)
Silk To Silk Clearance Constraint: (0.137mm < 0.254mm) Between Text "1" (49.428mm,116.427mm) on Top Overlay And Track (50.19mm,115.665mm)(50.19mm,120.745mm) on Top Overlay Silk Text to Silk Clearance [0.137mm]
Silk To Silk Clearance Constraint: (0.137mm < 0.254mm) Between Text "1" (99.388mm,116.452mm) on Top Overlay And Track (100.15mm,115.69mm)(100.15mm,120.77mm) on Top Overlay Silk Text to Silk Clearance [0.137mm]
Silk To Silk Clearance Constraint: (0.222mm < 0.254mm) Between Text "2" (48.92mm,118.967mm) on Top Overlay And Track (50.19mm,115.665mm)(50.19mm,120.745mm) on Top Overlay Silk Text to Silk Clearance [0.222mm]
Silk To Silk Clearance Constraint: (0.222mm < 0.254mm) Between Text "2" (98.88mm,118.992mm) on Top Overlay And Track (100.15mm,115.69mm)(100.15mm,120.77mm) on Top Overlay Silk Text to Silk Clearance [0.222mm]
Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "5" (108.024mm,116.452mm) on Top Overlay And Track (107.77mm,115.69mm)(107.77mm,120.77mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "5" (58.064mm,116.427mm) on Top Overlay And Track (57.81mm,115.665mm)(57.81mm,120.745mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "6" (108.024mm,118.992mm) on Top Overlay And Track (107.77mm,115.69mm)(107.77mm,120.77mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Silk To Silk Clearance Constraint: (0.052mm < 0.254mm) Between Text "6" (58.064mm,118.967mm) on Top Overlay And Track (57.81mm,115.665mm)(57.81mm,120.745mm) on Top Overlay Silk Text to Silk Clearance [0.052mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "IC1" (78mm,115.5mm) on Top Overlay And Track (79.1mm,117.25mm)(79.9mm,117.25mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (0.249mm < 0.254mm) Between Text "R1" (90mm,118.992mm) on Top Overlay And Track (88.679mm,118.516mm)(94.775mm,118.516mm) on Top Overlay Silk Text to Silk Clearance [0.249mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "Term_2" (100.339mm,103.888mm) on Top Overlay And Track (100.912mm,105.484mm)(100.912mm,107.516mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "Term_2" (100.339mm,103.888mm) on Top Overlay And Track (100.912mm,105.484mm)(107.008mm,105.484mm) on Top Overlay Silk Text to Silk Clearance [0mm]

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